Ic Design Verification Engineer R-10049768

OverviewThe Ottawa Technology Center, member of NXP MCU/MPU Engineering (MME) group, is a world-class team responsible for hardware and software development of some of the coolest embedded processing and networking products going into homes and businesses around the world. DescriptionThe hardware team is looking to hire a highly motivated design verification engineer with an insatiable desire to win and make an impact. We offer breakthrough thinking, engineering expertise, and sustained market leadership at the forefront of embedded processing. Joining this team will get you in contact with the cutting-edge platforms that NXP delivers to the major players in the Automotive, Industrial and telecommunication market:
multiple processing cores and high performance networking accelerators integrated on the same silicon chip. ResponsibilitiesDevelop solutions for the verification of the hardware System On Chip (SoC) products;
Develop, execute and debug a wide range of functional tests in a verilog simulation environment for content processing hardware IP designs;
Analyze requirements, Develop verification plans, test attributes and strategy;
Develop simulation environment, testcases, drivers, monitors and response checkers.Employ constrained random verification approaches when possible;
Analyze code coverage and address coverage issues;
Work closely with IC Design Engineers Key Qualifications10+ years of experience in constraint random verification, UVM verification and UVM environment development;
Proficient in test plan definition and testcase development in System Verilog;
Focus on quality of results, with proven problem-solving abilities;
Good understanding of coverage analysis, performance verification and use-case verification;
Fluency with scripting languages (e.G., Makefile, Perl, Python, Shell);
Ability to effectively communicate verbally and in writing in English and work within all levels of the organization;
Must be a dynamic team player;
The following skills arehighly desirable:
Familiar with Formal and Functional Safety verification;
Knowledge of L2 and L3 networking protocols implementation (e.G. Eth/IP/UDP);